Hybrid Simulation

VP and RTL running together in parallel

Hybrid Simulation

  • Hybrid Simulation enables a significant increase in simulation speed through parallel simulation of complex embedded hardware/software systems. The solution is based on parallel simulations using SystemC TLM2 combined with FPGA for fast and accurate emulation of hardware. The basis of this heterogeneous parallelization is the possibility to partition the SystemC simulation at transaction boundaries. The various design partitions are connected and synchronized by the RAVEN infrastructure.
  • In addition, the infrastructure enables parallel SystemC simulation of Loosely-Timed Virtual Prototypes.
  • Hybrid simulation can be performed on-premise or in a cloud. Hybrid Simulation Basic Structure

What is it good for?

  • Challenge
    A embedded project is rarely started from scratch. In most cases, there has already been a predecessor project, which will be partly reused. The problem is that there is no easy way to simulate RTL design together with a Virtual Prototype.
  • Problem with Traditional Methods
    SystemC can only be executed in a single process and does not benefit from modern multi-core processors. Moreover, OSCI SystemC does not provide the possibility to synchronize with FPGA simulation. It makes the SystemC simulator a performance bottle-neck for complex VP projects.
  • Solution:
    Hybrid simulation is interesting for customers who already have RTL and want to extend or replace part of the design (for example by introducing a RISC-V TGC core). Our solution enables parallel simulation of FPGA and SystemC. This allows our customers to easily simulate existing hardware in parallel with a virtual prototype.

Benifits and Features

Significant increase in simulation speed of complex designs:

  • Hardware and Virtual Prototype combined in Hybrid Simulation
  • Parallel Multi-Thread SystemC Simulation

More flexibility and better debug capabilities when integrating new components into an existing design.

Hybrid Featrures

Extended IEEE 1666-2011 SystemC TLM-2.0 Standards-Based Environment including:

  • Latest SystemC version (2.3.4) extended for multi-thread simulation.
  • Configuration, Control and Inspection (CCI) library that allows to instrument models so that a rich user experience is enabled.
  • SystemC Verification Library (SCV) for VP verification and TLM tracing.

Hybrid Simulation is completely integrated and fully combinable with other MINRES products and services like the open source SystemC Components (SCC) productivity library. Last but not least, our hybrid simulation solution allows cost savings combined with high reliability and scalability by enabling hybrid simulation in the AWS Cloud.