Alex Jentzsch – MINRES Technologies GmbH https://www.minres.com Thu, 04 Dec 2025 11:54:55 +0000 en-US hourly 1 https://wordpress.org/?v=6.8.1 https://www.minres.com/wp-content/uploads/2025/05/cropped-minres_favicon-32x32.png Alex Jentzsch – MINRES Technologies GmbH https://www.minres.com 32 32 NVIDIA’s AI chip dominance won’t last forever https://www.minres.com/nvidia-ai-chip-dominance-wont-last-forever/ Thu, 04 Dec 2025 11:26:27 +0000 https://www.minres.com/?p=3679

NVIDIA’s AI chip dominance won’t last forever

 

NVIDIA is throwing cash around yet again – this week buying a $2 billion stake in Synopsys, one of the EDA industry’s leading companies. This led me to reflect on my experience and observations from within the hardware industry.

Traditional business theory (and history) shows us that monopolies don’t sustain themselves over time: if a market is lucrative it inevitably attracts plenty of competition. Sometimes it’s overseen by anti-trust regulation.

Things are a little different when it comes to the industry of designing and manufacturing chips. Two factors lead me to this statement:

 

Firstly, the hardware design industry is one like no other, with deeply entrenched incumbents and oligopolies at almost every corner of the supply chain. In my line of work we see this in the three firms that dominate the EDA market. Decades in this same position give them incredibly solid defenses: deep moats and deep pockets! The only way into this market is when an even bigger organization has even deeper pockets (such as Siemens’ purchase of Mentor Graphics, the previous #3 in the EDA industry).

Secondly, hardware development is hard. And I mean really hard. Errors that are only detected late in development process are immensely costly. Over the years hardware has only become even bigger and more complex, and each piece of a complex system requires increasing amounts of specialization and deep expertise to create innovative products.

Combined with the lack of modern practices (why change, we have always been doing it this way) this means it takes serious effort and determination and, of course, funding to challenge the status quo.

 

Why the dogmatic headline then? Surely these arguments add weight to the idea that NVIDIA can hold onto its dominance in AI?

NVIDIA has shown the world that it’s possible to make eye-watering amounts of money from serving current and future high performance computing needs. And this makes it even more enticing for other companies to rise to the challenge. That could be companies with the existing financial means designing their own hardware for AI. Or it could be a new generation of companies with the objective of disrupting the market, backed by a fresh influx of capital funding.

The time to market for hardware is longer than for traditional software products – due in part to the reasons above. This buys NVIDIA more time to continue to spearhead the industry and reap the rewards of its past strategic decisions. New companies simply need a bit more time to organize themselves, to make a compelling business case to investors, to collect financial means and, ultimately to introduce a new product that excels in one aspect or another compared to the current state-of-the-art.

Today, the saving grace for the market leader is the difficulty of the challenges I mention above. But it is my firm belief that over the next few months and years we will see more and more small, highly specialized startups start to chip away and ultimately even challenge NVIDIA’s lead.

I would love to hear from you if you agree or if you have alternative predictions. Feel free to contact us or get involved in the conversation on LinkedIn.

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]]> Navigating Design Complexity and Choice of Simulator https://www.minres.com/navigating-design-complexity-and-choice-of-iss/ Thu, 19 Jun 2025 15:04:22 +0000 https://www.minres.com/?p=1991

Navigating Design Complexity and Choice of Simulator

On an almost daily basis, hardware designers are facing increasing complexity and difficulties in navigating their designs. An increased complexity inevitably leads to longer development times – delays to achieve a working prototype – and a delayed time to market, which is a serious impact on the business. A working prototype is essential for evaluating the functionality of the end system running the software, shaping hardware needs and forcing adaptations. It makes sense for a prototype to be developed quickly and readily adapted.

An industry-proven way to build these virtual prototypes is the use of simulator-based tools, such as the proprietary options from Synopsys and Cadence, or open-source options like SystemC or QEMU.

While there are scenarios where SystemC is the best choice, like when using Verilator or when having setup a SystemC UVM testbench, a designer may well find themselves without a core (or rather an Instruction set simulator) that can be easily integrated.

There are a lot of Instruction Set Simulators (ISSs) out there, each with their own advantages such as the riscv-isa-sim model written in SAIL as the golden reference model for RISC-V, or even QEMU known for its fast simulation speed and widespread adoption.

Integrating an ISS into SystemC can be really challenging if it was not designed for it. Some of the big Industry players have attempted to address this. In the case of QEMU it is called qbox, maintained by Qualcomm. However, a platform simulation can involve a lot of work: if there are mismatches in versions or if essential features are not supported.

The current approach often involves engineers spending considerable time and effort integrating QEMU into a SystemC simulation, construct its platform model and get all the relevant parts to talk to the other non-QEMU components. This is neither the best use of resources nor time.

DBT-RISE addresses this need: It offers effortless integration because it was written from the ground-up to be used as the core inside a platform level SystemC simulation. DBT-RISE is architecture agnostic and so far it has been used predominantly to run simulations on the RISC-V instruction set and a range of its extensions.

DBT-RISE is an open-source framework that is accompanied by open source implementations of RV32GC and RV64GC cores. Being written in C++, it easily allows developers to expand the functionality of the core, for example introducing new instructions or architectural states. DBT-RISE also offers full support of Dynamic Binary Translation, translating target code to host machine code, which means it increases simulation speed.

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