Introduction
The Good Folk Series from MINRES is a growing family of Trustworthy, Generator-Based and Flexible hardware IP, developed according to the safety standard ISO 26262.
The automated, software-driven IP development facilitates the optimization of the application algorithms. State-of-the-art development and verification techniques ensure not only meeting the customer requirements, but also delivering the highest quality. The concise documentation and exhaustive deliverables ensure a smooth integration into the target system.
The Good Core (TGC) is the first member of The Good Folk Series. It is a highly flexible, scalable and extendable processor that perfectly fits low-power applications in IoT or edge computing areas.
The Good Core Overview
TGC is based on the open RISC-V ISA and the growing ecosystem around it, which guarantees continuity and sustainability.
The 5 basic TGC configurations combine 3, 4 or 5 pipeline stages with different standard RISC-V instructions and additional features. Each of these cores can be optimised for area or performance and further customised.
Configurable features are the memory bus interfaces, which can be AHB3Lite, AXI4 or OBI 1.0, Core Local Interrupt Controller (CLIC), Physical Memory Protection (PMP), safety features, caches, branch prediction, debug capabilities and custom instructions,
TGC-A
The smallest core of the family targets state machine controllers with a 3-stage pipeline, 16 registers RV32E.
TGC-B
This 3-stage pipeline RV32I_Zicsr_Zifencei core is best suited for embedded systems.
TGC-C
This core is a 4-stage pipeline RV32IMC_Zicsr_Zifencei, which is RTOS capable.
TGC-D
In addition to the features in TGC_C, this core has CLIC and PMP capabilities to support a dense hw/sw interaction, while keeping the memory contents secure.
TGC-E
This core has a 5-stage pipeline and all the features in TGC_D, therefore can be used for high frequencies requirements.