Virtual Protyping (VP) is the proven methodology for early software development and architectural exploration. To verify the correctness of modeled IP, different levels of verifications are adopted. One favored, less resource-intensive verification methodology, is the direct comparison of the RTL design with its VP-level model.

With the existing verilog codes of the RTL design, MINRES has the experience to translate it into a desired corresponding model. In such situations, correlation between the RTL and the model is essential for evaluating the correctness and quality of the model. During correlation, the VP is compared against the RTL simulation, which acts as the golden reference.

The challenge of correlation here is to “see” the difference (as in literally looking at and spotting differences in waveforms), which could either stem from issues in the RTL or in the model, and to understand it properly. To analyze the behavior of the RTL simulation, looking into the waveform is necessary, which is very difficult and time-consuming for complicated scenarios.

We at MINRES continue to explore innovative approaches to address these issues.

The team has been researching automated waveform analysis to eliminate the need for manual verification of waveforms. To that end, we adopted the Waveform AnalysisLanguage (WAL), a recent development from the Institute for Complex Systems at Johannes Kepler University Linz (JKU) (ICS JKU).

After evaluating WAL, we discovered that it can significantly help us with our correlation challenges. By “surfing” over the RTL waveforms using a WAL program, we reconstruct VP- level transactions from the low-level signals in the waveform. Correlation between the RTL and the model is now much easier to do since both are at the same abstraction level.

Apart from correlation, we also used WAL to analyze the performance of our RISC-V cores. Given the growing adoption and interest in RISC-V, this capability promises significant benefits.

Through our collaboration with the WAL team at JKU, we’ve been able to accelerate and automate waveform analysis to uncover hidden bugs in the RTL design and to identify issues during architecture exploration.

Look out for my next post, in which I will look at how WAL can “surf” through the waveform for functional debugging. I will also talk about how the pipeline design of RISC-V processors can be improved with WAL.