Navigating Design Complexity and Choice of Simulator

On an almost daily basis, hardware designers are facing increasing complexity and difficulties in navigating their designs. An increased complexity inevitably leads to longer development times – delays to achieve a working prototype – and a delayed time to market, which is a serious impact on the business. A working prototype is essential for evaluating the functionality of the end system running the software, shaping hardware needs and forcing adaptations. It makes sense for a prototype to be developed quickly and readily adapted.

An industry-proven way to build these virtual prototypes is the use of simulator-based tools, such as the proprietary options from Synopsys and Cadence, or open-source options like SystemC or QEMU.

While there are scenarios where SystemC is the best choice, like when using Verilator or when having setup a SystemC UVM testbench, a designer may well find themselves without a core (or rather an Instruction set simulator) that can be easily integrated.

There are a lot of Instruction Set Simulators (ISSs) out there, each with their own advantages such as the riscv-isa-sim model written in SAIL as the golden reference model for RISC-V, or even QEMU known for its fast simulation speed and widespread adoption.

Integrating an ISS into SystemC can be really challenging if it was not designed for it. Some of the big Industry players have attempted to address this. In the case of QEMU it is called qbox, maintained by Qualcomm. However, a platform simulation can involve a lot of work: if there are mismatches in versions or if essential features are not supported.

The current approach often involves engineers spending considerable time and effort integrating QEMU into a SystemC simulation, construct its platform model and get all the relevant parts to talk to the other non-QEMU components. This is neither the best use of resources nor time.

DBT-RISE addresses this need: It offers effortless integration because it was written from the ground-up to be used as the core inside a platform level SystemC simulation. DBT-RISE is architecture agnostic and so far it has been used predominantly to run simulations on the RISC-V instruction set and a range of its extensions.

DBT-RISE is an open-source framework that is accompanied by open source implementations of RV32GC and RV64GC cores. Being written in C++, it easily allows developers to expand the functionality of the core, for example introducing new instructions or architectural states. DBT-RISE also offers full support of Dynamic Binary Translation, translating target code to host machine code, which means it increases simulation speed.