Introduction
The development of complex hardware/software systems is a time-consuming and resource-intensive process that requires extensive testing and verification. The growing complexity of the systems has made simulation for verification increasingly difficult and slow.
RAVEN allows to speed up SystemC simulations through coarse-grained parallelization. Even more important RAVEN infrastructure enables the co-simulation of SystemC and RTL mapped onto FPGA. The development of an embedded hardware project rarely starts from scratch. Typically, there are previous projects with reusable hardware components that should be integrated into the verification of new elements as soon as possible. Addressing this need, RAVEN aims to accelerate project development by enabling hybrid simulation. Hybrid simulation is a parallel simulation of a hardware design partly on FPGA and partly in SystemC. RAVEN enables the integration of existing RTL components using an FPGA, while simultaneously running new system components as a Virtual Prototype on the host.
RAVEN
RAVEN supports different simulation options to enable more efficient and accurate hardware/software development.
- Challenge
The development of an embedded hardware project rarely starts from scratch. Typically, there are previous projects with reusable hardware components that should be integrated into the verification of new elements as soon as possible. The problem is that there is no easy way to simulate RTL design together with a Virtual Prototype. - Problem with Traditional Methods
SystemC can only be executed in a single process and does not benefit from modern multi-core processors. Moreover, OSCI SystemC does not provide the possibility to synchronize with FPGA simulation. It makes the SystemC simulator a performance bottle-neck for complex VP projects. - Solution
Hybrid simulation is interesting for customers who already have RTL and want to extend or replace part of the design (for example by introducing a RISC-V TGC core). Our solution enables the integration of existing RTL components using an FPGA, while simultaneously running new system components as a Virtual Prototype on the host. This allows our customers to easily simulate existing hardware in parallel with a virtual prototype.
Hybrid Simulation is completely integrated and fully combinable with other MINRES products and services like the open source SystemC Components (SCC) productivity library. Last but not least, our hybrid simulation solution allows cost savings combined with high reliability and scalability by enabling hybrid simulation in the AWS Cloud.
Hybrid Simulation
RAVEN combines the advantages of SystemC simulation and FPGA prototyping in a ‘hybrid simulation’ capability.
The hybrid approach means RAVEN achieves the best acceleration, significantly reducing the time for simulations involving mixed abstraction..
Creating these hardware and software parts by hand would be both time-consuming and error-prone. RAVEN automates this process with RavenDSL which describes the interfaces of the RTL to be simulated.
RavenDSL is a domain-specific language and tool flow and is used to automatically create the hardware/software components required for an FPGA-based partition.
RAVEN offers developers the flexibility to run parallel and hybrid simulations either locally on-premise, or in the cloud. Cloud simulation provides scalable and cost-effective access to a wide range of computing resources and reduces the need for upfront investment in hardware and maintenance. A graphical user interface supports setup, configuration as well as operation of the simulation in the cloud.
RAVEN is compatible with the Accellera SystemC reference implementation to simplify integration into existing workflows, while its cloud-based capabilities enable flexible and scalable simulation environments.