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The Good Cores

A configurable family of RISC-V cores designed for efficient SoC integration, with the flexibility to tailor performance, power and silicon area to your application.

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The Good Cores (TGC)

At the heart of The Good Folk Series (TGFS) are The Good Cores (TGC), a highly flexible, scalable and extendable RISC-V core family from MINRES. TGC enable you to build exactly the SoC you need – no more, no less – resulting in better performance per watt and optimal silicon area usage. The open standard RISC-V ISA and the growing ecosystem around it guarantee the continuity and sustainability of the TGC IPs. It is best suited for low-power applications in IoT and edge applications.

TGC processors are available in five standard configurations, each available in 32-bit or 64-bit. They all are Harvard, single issue in-order pipelines, with either 3, 4 or 5 stages.

TGC*A

The smallest core of the TGC family targets state machine controllers. It is best suited for embedded systems with low power and low area requirements.

  • RV32E or RV64E Zicsr Zifencei (16 GPR)
  • 3 stage, single issue in-order pipeline
  • No caching or branch prediction
  • Machine mode only
  • CLINT and wait for interrupt (WFI) support
  • Memory bus interface: AHB3 Lite, AXI4, AXI4Lite, OCP, and OBI 1.0

TGC*B

This 3-stage pipeline RV32I or RV64I core is best suited for embedded systems as it supports RTOS, still having reduced area and power consumption.

  • RV32I or RV64I Zicsr Zifencei
  • 3 stage, single issue in-order pipeline
  • Machine mode only
  • CLINT & wait for interrupt (WFI) support
  • Memory bus interface: AHB3 Lite, AXI4, AXI4Lite, OCP, and OBI 1.0

TGC*C

For Edge and IoT applications, this 4-stage RV32IMC or RV64IMC core offers the basic capabilities.

  • RV32IMC or RV64IMC Zicsr Zifencei
  • Machine mode only
  • 4 stage, single issue in-order pipeline
  • CLINT & wait for interrupt (WFI) support
  • Memory bus interface: AHB3 Lite, AXI4, AXI4Lite, OCP, and OBI 1.0

TGC*D

When dense hardware-software coupling is required for Edge and IoT applications, this 4-stage RV32IMC or RV64IMC core integrates configurable and extendable CLIC and PMP capabilities.

  • RV32IMC or RV64IMC Zicsr Zifencei
  • Machine & User mode
  • 4 stage, single issue in-order pipeline
  • CLIC + wait for interrupt (WFI) support
  • Memory bus interface: AHB3 Lite, AXI4, AXI4Lite, OCP, and OBI 1.0
  • Physical memory protection (PMP)

TGC*E

The largest of the standard configurations is the choice for IoT or Edge applications with high frequency requirements. It has the capabilities of TGC*D in a 5-stage pipeline.

  • RV32IMC or or RV64IMC Zicsr Zifencei
  • Machine & User mode
  • 5 stage, single issue in-order pipeline
  • No caching or branch prediction
  • CLIC + wait for interrupt (WFI) support
  • Memory bus interface: AHB3 Lite, AXI4, AXI4Lite, OCP, and OBI 1.0
  • Physical memory protection (PMP)

Optional features:

Many other helpful features can be integrated if required:

  • LR/SC support (part of A extension)
  • Custom instructions
  • Non-maskable interrupts (NMI)
  • Safety features: ECC, parity and lockstep
  • Cache support
  • Branch prediction
  • Trace and debug capabilities
  • Hart to encoder trace interface
  • User mode (U extension)
  • User level interrupts (tentatively reserved N extension)

Moonlight subsystem for RISC-V

You’ve chosen your TGC processor core, now it’s time to build the system…read about about Moonlight can help accelerate your development. Read the white paper to understand how Moonlight provides an ideal development framework for high-reliability RISC-V systems

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