RISC-V Tournament: Come Join The Battle of HDLs

In our previous post, Pipelined RISC-V in RHDL, we described how we translated an existing VHDL implementation of a pipelined RISC-V processor into RHDL, synthesized it, and ran it on an FPGA. That experiment was the first step in a broader plan: comparing modern hardware description approaches on realistic designs – and under conditions that […]