In our previous post, Pipelined RISC-V in RHDL, we described how we translated an existing VHDL implementation of a pipelined RISC-V processor into RHDL, synthesized it, and ran it on an FPGA.
That experiment was the first step in a broader plan: comparing modern hardware description approaches on realistic designs – and under conditions that are as transparent and reproducible as possible.
Last week at the RISC-V Summit Europe in Bologna, we presented the next step in that effort: the RISC-V Tournament: Battle of HDLs.
The tournament is now up-and-running — and we invite you to get involved. Read on to find out how…
The motivation is simple. Today’s HDL landscape is broader than ever. Alongside established RTL languages such as VHDL, Verilog, and SystemVerilog, there are HLS-based approaches and newer generative HDLs such as Chisel, SpinalHDL, Clash, RHDL, Amaranth, Spade, and others.
Many of these approaches promise better abstraction, improved reuse, higher productivity, or cleaner verification. But direct comparisons can be difficult when each evaluation uses a different design, different tool flow, and a different set of assumptions.
The RISC-V Tournament addresses this by creating a common arena.
All participants implement the same baseline RISC-V microarchitecture, based on a simple pipelined processor with memory interfaces and a lightweight GPIO peripheral driving LEDs. Functional correctness is checked using selected tests from the official RISC-V Architectural Test Suite. Qualified implementations are then synthesized using the open-source OSS CAD Suite, allowing metrics such as area, timing, and resource utilization to be compared under consistent conditions.
We should be clear: the goal here is not to declare one universal “best HDL”. Instead, the tournament should make trade-offs visible: where a language helps, where it gets in the way, and how different design approaches behave when applied to the same hardware problem.
The tournament is hosted on GitHub: https://github.com/Minres/riscv-tournament
Participation follows a simple workflow:
Fork the repository, implement or improve a core in your HDL of choice, run the provided test and synthesis flow, and compare the results. If your implementation improves the outcome while satisfying the architectural and verification requirements, submit a pull request.
After review, accepted improvements become part of the arena and serve as the new reference point for future contributions.
We want the Tournament to be iterative and community-driven. HDL experts can demonstrate the strengths of their preferred approach, while the wider community gains a growing set of public, reproducible reference implementations.
The RISC-V Tournament is active now. If you work with VHDL, Verilog, SystemVerilog, Chisel, SpinalHDL, Clash, RHDL, Amaranth, Spade, or another HDL or hardware construction language, we invite you to participate.
Bring your HDL into the arena, run it through the same tests and synthesis flow, and help build a transparent basis for comparing modern hardware design methodologies.
Let the battle of HDLs begin.
