The Good Folk Series

Trustworthy Generator-based Flexible and Scalable IPs

Accelerate SoC Development with MINRES Flexible, Scalable IP

At MINRES, we empower engineering teams to build better System-on-Chip (SoC) solutions – faster and with greater confidence. The MINRES flexible RISC-V processor cores, development frameworks, and our deep architectural know-how enable you to accelerate development and reduce risks at every stage.

Why Development Teams Choose MINRES hardware IP

MINRES software-driven approach boosts productivity and speed
Accelerated time-to-market through reusable IP and tooling
Open standard RISC-V ISA cores for long-term independence and ecosystem support
EDA-vendor agnostic implementation
Backed by modern verification methods and concise documentation

The Good Folk Series

The Good Folk Series (TGFS) is a growing family of trustworthy, generator-based and flexible hardware IP, created to offer reliable IP solutions tailored to exactly meet the system requirements. Each IP block is designed to integrate seamlessly into your project, reducing development effort and ensuring performance exactly where it matters most.

The innovative software-driven hardware IP is developed with state-of-the-art processes and tools and a strong focus on methodological competence and quality that are key elements of our company culture. Safety and security awareness at each step ensure operational integrity, full transparency and traceability throughout the IP life-cycle. High quality deliverables and concise documentation facilitate the IP integration into the target system.

The Good Folk Series Consists of 3 Building Blocks:

The Good Cores (TGC): A family of flexible RISC-V processor cores
Moonlight: A configurable and extendable subsystem, which complements TGC with memories, an interconnect infrastructure as well as various peripherals and controllers
The Good Accelerator (TGA): A generator-based machine learning accelerator

The Good Cores (TGC)

At the heart of The Good Folk Series (TGFS) are The Good Cores (TGC), a highly flexible, scalable and extendable RISC-V core family from MINRES. TGC enable you to build exactly the SoC you need – no more, no less – resulting in better performance per watt and optimal silicon area usage. The open standard RISC-V ISA and the growing ecosystem around it guarantee the continuity and sustainability of the TGC IPs. It is best suited for low-power applications in IoT and edge applications.

TGC processors are available in five standard configurations, each available in 32-bit or 64-bit. They all are Harvard, single issue in-order pipelines, with either 3, 4 or 5 stages.

TGC*A

The smallest core of the TGC family targets state machine controllers. It is best suited for embedded systems with low power and low area requirements.

Details

RV32E or RV64E Zicsr Zifencei (16 GPR)
3 stage, single issue in-order pipeline
No caching or branch prediction
Machine mode only
CLINT and wait for interrupt (WFI) support
Memory bus interface: AHB3 Lite, AXI4, AXI4Lite, OCP, and OBI 1.0

TGC*B

This 3-stage pipeline RV32I or RV64I core is best suited for embedded systems as it supports RTOS, still having reduced area and power consumption.

Details

TGC*C

For Edge and IoT applications, this 4-stage RV32IMC or RV64IMC core offers the basic capabilities.

Details

TGC*D

When dense hardware-software coupling is required for Edge and IoT applications, this 4-stage RV32IMC or RV64IMC core integrates configurable and extendable CLIC and PMP capabilities.

Details

RV32IMC or RV64IMC Zicsr Zifencei
Machine & User mode
4 stage, single issue in-order pipeline
CLIC + wait for interrupt (WFI) support
Memory bus interface: AHB3 Lite, AXI4, AXI4Lite, OCP, and OBI 1.0
Physical memory protection (PMP)

TGC*E

The largest of the standard configurations is the choice for IoT or Edge applications with high frequency requirements. It has the capabilities of TGC*D in a 5-stage pipeline.

Details

RV32IMC or or RV64IMC Zicsr Zifencei
Machine & User mode
5 stage, single issue in-order pipeline
No caching or branch prediction
CLIC + wait for interrupt (WFI) support
Memory bus interface: AHB3 Lite, AXI4, AXI4Lite, OCP, and OBI 1.0
Physical memory protection (PMP)

Optional features:

Many other helpful features can be integrated if required:

Details

LR/SC support (part of A extension)
Custom instructions
Non-maskable interrupts (NMI)
Safety features: ECC, parity and lockstep
Cache support
Branch prediction
Trace and debug capabilities
Hart to encoder trace interface
User mode (U extension)
User level interrupts (tentatively reserved N extension)

Moonlight subsystem for RISC-V

For applications and projects that require complete subsystems, MINRES offers Moonlight – a configurable and extendable subsystem built around a TGC. Moonlight lets you jumpstart development with a pre-integrated, pre-verified foundation, reducing setup times and simplifying project scoping.

One practical application is using Moonlight as a housekeeping system for a bigger SoC: It acts as the first entry point on boot, setting up and configuring the rest of SoC system. During operation, it can be used for monitoring operations. It can also act as the central peripheral provider on the SoC.

At the heart of Moonlight, a freely customizable TGC core offers the processing capabilities, complemented by memory, an interconnect infrastructure and various peripherals and controllers.

This overall composition of Moonlight can be tailored to your specific requirements.

The Interconnect System connects TGC with the rest of the subsystem with support for bus protocols including AXI4, AHB3, APB, AXI4Lite, OBI, OCP.

It can also be implemented using multiple interconnects: for example one high-speed bus connected to TGC, the main memory and other components that require high throughput like the DMA engine.
And a second lower-speed, area-optimized bus that connects the rest of the peripherals and components; a bridge connects it to the main bus, providing the required protocol conversions.

The memory system typically contains the main memory (implemented using SRAM), but can also include options like ROM.

We have a selection of standard peripherals available :

High-speed interfaces: Ethernet, (Quad-)SPI incl. XIP, USB(2/3)

Low-speed interfaces: UART, I2C/I3C, GPIO, I2S
Other utilities: Timer/Counter, PWM

Other peripherals, including custom, can be integrated where required. Moonlight also enables the integration of additional components like DMA or interrupt controllers.

This configurability and flexibility of Moonlight is enabled by a generator-based approach, which allows for a fast composition of the target system by selecting the required components as well as quickly integrating project-specific IPs, e.g., targeting machine learning applications like The Good Accelerator (TGA).

Moonlight white paper

MINRES Moonlight white paper available to download

A Development Framework for High-Reliability RISC-V Subsystems

Click to download the Moonlight paper

or contact us to find out more about how MINRES Moonlight can simplify your RISC-V development requirements.

What’s Next in The Good Folk Series?

The Good Accelerator for Edge AI/ML Applications

The Good Accelerator (TGA) is a flexible hardware IP block that offloads demanding deep neural network functions from the CPU, lowering power usage and freeing up processing capacity, ideal for Edge AI / Machine Learning applications. It is loosely coupled, so it can be combined with any processor. It supports both standalone and joint use with other components of The Good Folk Series. Using a generator-based approach, TGA creates customized hardware models that match specific applications, making it easier to optimize both the ML model and the hardware together. This allows you to build AI-enabled SoCs that deliver high performance without draining your power budget.

Coming soon, please register your interest.

Build Smarter

With The Good Folk Series and the MINRES methodology, your team stays in control, while gaining speed, safety, and structure. Whether you need a fast proof of concept or a robust product-grade SoC, our approach helps you deliver on time and at scale.

Get in touch to explore how we can support your next SoC project.