Empowering Better SoC Design

Our Customers and Partners

Our Approach

Virtual Prototyping and Platform Modeling

Target Application

Platform Model

PySysC

Custom Models

written by the customer

DBT-Rise, QEMU

SystemC/
TLM2.0

C++

Insights

DVCon Europe 2025: Arteris, MINRES and the Fraunhofer Institute present improvements to SoC modeling and architectural exploration

DVCon Europe 2025: Arteris, MINRES and the Fraunhofer Institute present improvements to SoC modeling and architectural exploration

  DVCon Europe October 14, 11:30 AM – 1:00 PM | Forum 5 | 2BEfficient SoC Modeling, Architectural Exploration, and…

My Journey as a Working Student at MINRES

My Journey as a Working Student at MINRES

When I look back at my journey at MINRES Technologies GmbH from July 2024 to August 2025, I realize how…

Debug. And Trace. They’re not always two sides of the same coin

Debug. And Trace. They’re not always two sides of the same coin

A recent MINRES project with Accemic made me stop and think about how debug and trace are often lumped together…

DVCon Europe 2025: Arteris, MINRES and the Fraunhofer Institute present improvements to SoC modeling and architectural exploration

DVCon Europe 2025: Arteris, MINRES and the Fraunhofer Institute present improvements to SoC modeling and architectural exploration

  DVCon Europe October 14, 11:30 AM – 1:00 PM | Forum 5 | 2BEfficient SoC Modeling, Architectural Exploration, and…

My Journey as a Working Student at MINRES

My Journey as a Working Student at MINRES

When I look back at my journey at MINRES Technologies GmbH from July 2024 to August 2025, I realize how…

Debug. And Trace. They’re not always two sides of the same coin

Debug. And Trace. They’re not always two sides of the same coin

A recent MINRES project with Accemic made me stop and think about how debug and trace are often lumped together…