DVCon Europe 2025: Arteris, MINRES and the Fraunhofer Institute present improvements to SoC modeling and architectural exploration

  DVCon Europe October 14, 11:30 AM – 1:00 PM | Forum 5 | 2BEfficient SoC Modeling, Architectural Exploration, and…

My Journey as a Working Student at MINRES

When I look back at my journey at MINRES Technologies GmbH from July 2024 to August 2025, I realize how…

Debug. And Trace. They’re not always two sides of the same coin

A recent MINRES project with Accemic made me stop and think about how debug and trace are often lumped together…

There’s a Lot More to Rust Than Memory Safety

In the last couple of years the Rust programming language has gained an ever-growing mind-share amongst developers, companies and even…

Unlocking the Power of Virtual Platforms in SoC Development: From Pre- to Post-Silicon

As System-on-Chip (SoC) designs become increasingly complex, development teams are under growing pressure to deliver high-performance, software-rich silicon solutions with…

RISC-V is a shifting but consistently growing ecosystem – particularly in Europe

Although RISC-V started life over 15 years ago, its prominence and the magnitude of its potential threat to proprietary ISAs…

Remote Teamwork is Alive and Well

The merits of traditional office-based versus virtual, remote teams continues. It would appear that the opposing views are not solely…

Finding Hidden Issues with Innovative Methodological Approaches

Virtual Protyping (VP) is the proven methodology for early software development and architectural exploration. To verify the correctness of modeled…

Navigating Design Complexity and Choice of Simulator

On an almost daily basis, hardware designers are facing increasing complexity and difficulties in navigating their designs. An increased complexity…