A German FPGA and a synthesis tool with Austrian roots—sounds like the beginning of a European hardware collaboration. And in a way, that’s exactly what Cologne Chip’s GateMate represents.
The FPGA market has long been dominated by manufacturers such as AMD/Xilinx, Intel/Altera, and Lattice, with Gowin increasingly competing in the low-cost segment. Cologne Chip is a German semiconductor manufacturer offering an interesting European alternative with its GateMate FPGA family. Although at MINRES we partner with companies from around the globe, we are always interested to support the European chip industry.
What makes GateMate particularly interesting is not necessarily its raw performance, but its combination of hardware capabilities, open-source development tools, plus its European roots.
The GateMate A1 is manufactured (by GlobalFoundries in Dresden) using a 28 nm process. It provides 20,480 configurable logic elements, 1,280 Kbit of block RAM, four PLLs, and a 5 Gbit/s SerDes interface.
Particularly noteworthy is GateMate’s I/O connectivity. With up to 162 GPIO signals, the FPGA offers considerable flexibility for connecting external peripherals and implementing custom interfaces. The evaluation board exposes 108 GPIOs, making it attractive for hardware prototyping.
Another important aspect is its development ecosystem. GateMate supports Yosys, originally developed by Austrian engineer Claire Wolf, for synthesis, alongside nextpnr for place-and-route and openFPGALoader for programming.
This German–Austrian collaboration provides a European-rooted FPGA development workflow without relying on proprietary vendor software.
Open-source FPGA development is not unique to GateMate. Lattice’s iCE40 and ECP5 families have supported similar workflows for years. Gowin offers competitively priced FPGA boards, while AMD/Xilinx provides mature development environments, extensive IP libraries, and devices covering a much broader performance range.
In terms of price, GateMate’s evaluation board is not the cheapest option. However, comparing FPGA boards purely by price or logic element count can be misleading. Architectural differences, available memory, I/O connectivity, and peripheral interfaces all influence their suitability for particular applications.
GateMate also has its limitations. Compared to established FPGA families, GateMate’s smaller ecosystem does mean there are fewer readily-available IP cores, examples, and a smaller pool of community resources.
At MINRES, we use the GateMate Starter Kit as the hardware platform for our RISC-V Tournament: Battle of HDLs .
The tournament compares different hardware description languages using a common RISC-V processor architecture, standardized verification, and a reproducible implementation flow. GateMate’s open-source toolchain fits particularly well into this approach, allowing implementations to be evaluated under consistent conditions.
While GateMate may not compete with every established FPGA family in terms of ecosystem maturity or available resources, it certainly provides an interesting platform for experimentation and development. And we do think there is something rather fitting about running a RISC-V tournament using a German FPGA and a synthesis tool with Austrian roots. It may not be an entirely European toolchain, but it certainly demonstrates that there is a growing sovereignty in the European semiconductor industry, and interesting FPGA development does not always have to depend exclusively on the traditional semiconductor industry players.
