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RISC-V Tournament: Come Join The Battle of HDLs

In our previous post, Pipelined RISC-V in RHDL, we described how we translated an existing VHDL implementation of a pipelined RISC-V processor into RHDL, synthesized it, and ran it on an FPGA. That experiment was the first step in a broader plan: comparing modern hardware description approaches on realistic designs – and under conditions that […]

Supply Chain Security Part 2: Mitigating Attacks

This is the second part of a series touching on issues related to supply chain security. In the first part of this series “Supply Chain Security for Developers” I talked about the trust we place in the countless dependencies and tools that make up our software development environments. I explored how this web of trust […]

Embedding Lifecycle Security to build European Sovereignty in AI and Defense

Embedded system designers today face a security landscape that is broader, more physical, and more time-sensitive than ever before. The ‘traditional’ threats still matter: malware, insecure firmware updates, weak authentication, memory corruption, supply-chain compromise, and unauthorized access can all undermine devices that control vehicles, industrial plants, medical equipment, defense platforms, and AI accelerators. But, this […]

Pipelined RISC-V in RHDL: A Five-Stage Journey Through Hazards and Stalls

At MINRES, we are always trying to find ways to improve hardware design productivity, verification workflows, and system-level integration – and in doing so end up evaluating a lot of emerging technologies. We have recently been working on one that we would like to share: we translated an existing VHDL implementation of a pipelined RISC-V […]

Implementing ISO 9001 as a small company: why it’s worth it

Choosing to pursue certification to a standard like ISO 9001 can look like a lot of work and an unnecessary burden, particularly to a small company: a lot of effort, documentation, and lots of money. Is that investment in vain? I don’t think so. ISO 9001 is all about improving consistency in your processes, reducing […]

Bridging Worlds: SystemC TLM Meets Verilated RTL

In modern hardware design, systems evolve through multiple levels of abstraction before reaching silicon. Each stage adds more detail, constraints, and implementation accuracy. In the early stages, engineers focus on functionality and architecture exploration and SystemC TLM (Transaction-Level Modeling) plays an important role. Fast simulation speeds allow designers to evaluate architectural decisions and communication schemes […]

Building Scalable Edge Intelligence with Scale4Edge and RISC-V

Modern edge devices power everything from industrial IoT systems to advanced automotive sensor processing. With shifts from centralized cloud infrastructures to processing data directly at the source, new challenges emerge: constraints on performance, power consumption, safety, and security. At the same time, reducing latency and bandwidth usage has become critical. These demands call for scalable, […]