DVCon Europe 2025: Arteris, MINRES and the Fraunhofer Institute present improvements to SoC modeling and architectural exploration

DVCon Europe 2025: Arteris, MINRES and the Fraunhofer Institute present improvements to SoC modeling and architectural exploration

DVCon Europe

October 14, 11:30 AM – 1:00 PM | Forum 5 | 2B
Efficient SoC Modeling, Architectural Exploration, and Result Analysis using TLM2-based IPs
Presented by Rocco Jonack of MINRES Technologies GmbH (and representing Arteris), and Matthias Jung of Fraunhofer IESE
Program: https://dvcon-europe.org/program/2025/2025-tutorials

The tutorial at DVCon will demonstrate how the collaboration of the three companies (MINRES Technologies, Arteris and Fraunhofer IESE), provides efficient modeling solutions for modern SoC development.
Modeling is one of those topics which requires collaboration to enable integration. Open-source based standards and ISAs, like RISC-V, play an increasingly important role in the development process. The tutorial will demonstrate examples along those lines.

The tutorial addresses the critical need for efficient modeling, comprehensive architectural exploration, and insightful result analysis within the constraints of typical project lifecycles.

The increasing availability and maturity of pre-verified IP blocks, such as CPUs, DRAM controllers, and interconnect fabrics, present an opportunity to shift the focus from low-level component modeling to system integration. By leveraging these readily available IPs, designers can concentrate on the critical aspects of system architecture, inter-component communication, and overall system behavior.

This tutorial aims to bridge the gap between theoretical modeling techniques and practical SoC design workflows. We will explore strategies for accelerating the initial model generation process, enabling designers to rapidly prototype and evaluate different architectural configurations.

A key aspect of this tutorial is the usage of architectural exploration techniques. This will involve the use of simulation-based techniques to evaluate the impact of different architectural choices, such as the number and type of key initiators like CPUs, video processing units or accelerators, the memory hierarchy configuration, and the interconnect topology.

Specifically, the tutorial will cover the following key topics:

Seamless integration of components into a unified platform: We will explore techniques for assembling and configuring a system-level model from individual IP components. In a discussion of the challenges of inter-component communication and synchronization we will explore different approaches for modeling these interactions.
Illustrative platform examples and their associated use models: This section will present several real-world SoC architectures, showcasing different design choices and their impact on system performance.
Analysis of model simulation results: This section will focus on the techniques for extracting meaningful insights from simulation data. We will discuss methods for visualizing and analyzing performance metrics and resource utilization statistics. We will also explore strategies for generating flexible reports that can be tailored to the specific needs of different stakeholders.

Hope to see you there.

Duration – 90 minutes

Program information:

Organizer: Rocco Jonack, MINRES Technologies GmbH

Speakers:

Rocco Jonack, MINRES Technologies GmbH

Matthias Jung, Fraunhofer IESE

(Support from Jean-Blaise Pierres, Arteris)

Are you attending DVCon and interested in meeting with MINRES?