RISCV – MINRES Technologies GmbH

Christoph Hazott

Pipelined RISC-V in RHDL: A Five-Stage Journey Through Hazards and Stalls

At MINRES, we are always trying to find ways to improve hardware design productivity, verification workflows, and system-level integration – and in doing so end

May 7, 2026

Johannes Wirth

Flexible Embedded AI for Automotive Systems: Hardware-Independent DNN Deployment with RISC-V

Modern automotive systems feature a range of sensors and cameras, providing input to driver assistance systems. Deep Neural Networks (DNNs) executed in embedded AI platforms

February 3, 2026

Rocco Jonack

DVCon Europe 2025: Arteris, MINRES and the Fraunhofer Institute present improvements to SoC modeling and architectural exploration

DVCon Europe October 14, 11:30 AM – 1:00 PM | Forum 5 | 2BEfficient SoC Modeling, Architectural Exploration, and Result Analysis using TLM2-based IPsPresented by Rocco

October 2, 2025

Pipelined RISC-V in RHDL: A Five-Stage Journey Through Hazards and Stalls
Implementing ISO 9001 as a small company: why it’s worth it
Bridging Worlds: SystemC TLM Meets Verilated RTL
Building Scalable Edge Intelligence with Scale4Edge and RISC-V
Integrating QEMU in SystemC Virtual Platforms: why official library support would make it easier